The present invention is directed, in general, to data bus architectures and, more specifically; to a circuit and protocol for synchronizing data transfers on a TDM bus architecture.
The present invention is related to that disclosed in U.S. patent application Ser. No. 09/164,925, entitled xe2x80x9cCOMMUNICATION BUS ARCHITECTURE FOR INTERCONNECTING DATA DEVICES USING SPACE AND TIME DIVISION MULTIPLEXING AND METHOD OF OPERATIONxe2x80x9d and filed on Oct. 1.1998. U.S. patent application Ser. No. 09/164,925 is commonly assigned with the present invention and is incorporated herein by reference for all purposes.
Information systems have evolved from centralized mainframe computer systems supporting a large number of users to distributed computer systems based on local area network (LAN) architectures. As the cost-to-processing-power ratios for desktop PCs and network servers have dropped precipitously, LAN systems have proved to be highly cost effective. As a result, the number of LANs and LAN-based applications has greatly increased.
A consequential development relating to the increased popularity of LANs has been the interconnection of remote LANs, computers, and other equipment into wide area networks (WANs) in order to make more resources available to users. This allows LANs to be used not only to transfer data files among processing nodes in, for example, an enterprise (i.e., privately owned) network, but it also allows LANs to be used to transfer voice and/or video signals in, for example, the public telephone networks. However, a LAN backbone can transmit data between users at high bandwidth rates for only relatively short distances. In order to interconnect devices across large distances, different communication protocols have been developed. These include X.25, ISDN, frame relay, and ATM, among others.
Most data transmissions, including file transfers and voice, occur in bursts at random intervals. The bursty nature of most data transmissions means that if the bandwidth allocated to a transmitting device is determined according to its peak demand, much bandwidth is wasted during the xe2x80x9csilencesxe2x80x9d between data bursts. This variable bandwidth demand problem has been solved in part by X.25, frame relay and ATM, which use statistical multiplexing to improve the throughput of multiple users.
In order to allow dissimilar protocol devices, such as frame relay systems and ATM systems, and different speed data lines, such as T1 and T3, to communicate with one another, a host of well-known interfaces have been developed to interconnect the dissimilar devices. For example, frame relay-to-ATM interfaces have been developed that include a high-level data link control (HDLC) interface for sending and receiving frames to and from a frame relay-based network and a segmentation and reassembly (SAR) interface for sending and receiving cells to and from an ATM-based network.
It is therefore common to find networks containing a mixture of interconnected, diverse protocol devices, such as frame relay devices and ATM devices, communicating with one another via a high-speed backbone network. To access this high-speed backbone network, it is common practice to employ multiplexers at or near the periphery of a network to receive lower speed data transfers from a group of devices and/or sub-networks. To increase the effective throughput of this access (i.e., the utilization of the backbone network) access concentrators commonly replace these access multiplexers. Besides access multiplexing, access concentrators use semiconductor memory to permit the peak access bandwidth (i.e., the peak aggregate bandwidth of the access ports) to actually exceed the peak available bandwidth of the backbone circuit. This is done under the assumption that, under ordinary circumstances, not all of the input lines transmit simultaneously and, when the input lines do transmit simultaneously, it is for a short period of time (i.e., statistical multiplexing).
A communication network that includes data transport links that are operating at nominally the same primitive frequency, but still asynchronously (i.e., almost synchronous), is referred to as a plesiochronous network. A digital network which uses a strict or fixed set of frequencies to multiplex a fixed primitive frequency is referred to as a digital hierarchy. A digital hierarchy of plesiochronous primitives is referred to as a plesiochronous digital hierarchy (PDH). A PDH network typically includes a discrete number of fixed data rates in which the rates of all data lines are a multiple of a base rate. For example, in North America, a T1 line carries twenty-four (24) of the basic (DS0) rate channels of 64 Kbps and a T3 line carries a DS3 rate channel of 28 (T1) or 672 (DS0). Multiple T1, lines can therefore be multiplexed into a T3 line, with each of the T1 lines operating at different clock speeds. PDH networks typically use a highly accurate clock, such as a cesium clock, as a master clock to overcome problems inherent in multiplexing data lines from multiple sources within a network having different primitive data rates.
Many concentrators and other communications devices, such as multiplexers, switches, routers, bridges, etc., contain interconnection circuitry designed to direct input signals received by a group of input port devices to a group of output devices, such as protocol processors. Frequently, the internal interconnection circuitry takes the form of a multiplexer that receives signals from a variable number of interface lines (i.e., multi-source) and directs the composite aggregate signal over a single wire to one or more destinations.
Additionally, the serial data transferred on a bus line typically is buffered in the receiving interface before further processing takes place. The size of the receiving data buffer is usually determined by the size of the incoming frames. For example, in a T1 interface, the receiving buffers are frequently sized to store an entire or even multiple sequential instances of the 193-bit frame received from the interconnection bus architecture. This is true even if the protocol processing engines that process the data stored in the receiving buffers are only 32-bit processors. The larger the receiving data buffers are, the larger and more complex are the line interface cards.
There is therefore a need in the art for improved TDM serial communications and synchronization techniques for use in a plesiochronous communications device that performs high-speed data multiplexing and de-multiplexing of asynchronous framed data streams. In particular, there is a need for a synchronization circuit and a synchronization protocol that minimizes the complexity involved in synchronizing data transfers in a plesiochronous digital hierarchy. More particularly, there is a need for a synchronization circuit and a synchronization protocol that minimize or eliminate the number of clock lines needed in a bus architecture that interconnects a plurality of data drivers and a plurality of data receivers. Finally, there is a need for a synchronization circuit and a synchronization protocol that minimize the memory requirements of the interface circuitry that transfers the data across a serial TDM medium.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in a communication device, a data transfer system comprising: 1) a frame data interface circuit capable of receiving incoming data frames from a plurality of frame data sources; and 2) a transmit buffer coupled to the frame data interface circuit and receiving the incoming data frames therefrom, wherein the transmit buffer is capable of dividing a first selected incoming data frames into a plurality of N-bit data fields and attaching to each of the plurality of N-bit data fields a M-bit control field comprising a synchronization indicia associated with the first selected incoming data frame, each N-bit data field and the attached M-bit control field comprising a data record. The data transfer system further comprises a receive buffer coupled to the transmit buffer and receiving the data records therefrom, wherein the receive buffer is capable of re-assembling the first selected incoming data frame from selected ones of the received data records and generating from the synchronization indicia therein a timing signal associated with the first selected incoming data frame.
According to another embodiment of the present invention, the first selected incoming data frame comprises a T1 frame received from a T1 line coupled to the frame data interface circuit.
According to another embodiment of the present invention, the synchronization indicia comprises a frame marker indicating a boundary of the T1 frame.
According to still another embodiment of the present invention, a first M-bit control field in a first selected data record indicates where in a first N-bit data record in the first selected data record the frame marker is located.
According to yet another embodiment of the present invention, the synchronization indicia comprises a synchronous residual time stamp.
According to a further embodiment of the present invention, the first selected incoming data frame comprises a T3 frame received from a T3 line coupled to the frame data interface circuit.
According to a still further embodiment of the present invention, at least one of the incoming data frames received by the frame data interface circuit is received at a first bit data rate and at least one of the incoming data frames received by the frame data interface circuit is received at a second bit data rate different than the first bit data rate.
According to a yet further embodiment of the present invention, the incoming data frames received by the frame data interface circuit comprise T1 frames and T3 frames
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.